Better understanding and control of residual stress in the chip build-up layer are becoming more and more important for the assembly process. To estimate the chip warpage and characterize the residual stress, different methods are proposed. However, most of them have high cost or some limitations for the upper build-up material. In this study, an innovative method is proposed to characterize the residual stress and predict the chip warpage behavior of different size chips at different temperatures. The method combines experimental inspection of chip warpage and finite element analysis. By reducing the silicon die thickness, the influence of residual stress in the build-up layer can be amplified. The residual stress can be obtained by inspecting the increased warpage when the silicon dies are reduced to different thicknesses. Correlating the thermal increase warpages of thinner chips can help characterize the effective modulus and coefficient of thermal expansion (CTE) of the build-up layer. This study can help better understand the commonly classified build-up layer information. The results show good agreements between two types of samples under the same upstream process flow.