A design methodology is developed for a linear, uncertain, SISO system for maximizing the size of a step disturbance in the presence of hard time domain constraints on system states, control input, output and the bandwidth. It is assumed that the system dynamics can be represented by a combination of structured uncertainty in the low frequencies and unstructured uncertainty in the high frequencies. The design procedure is based on mapping the time domain constraints into an equivalent set of frequency domain constraints which are then used to determine an allowed design region for the nominal loop transfer function in the plane of amplitude-phase. Once such a region is found, classical loop shaping determines a suitable nominal loop transfer function. The pole-zero structure of the compensator is a natural consequence of loop shaping and is not preconceived. An illustrative example demonstrates the trade-off between controller bandwidth, or the cost of feedback, and the tolerable size of step disturbance.
Frequency Domain Design for Maximizing the Allowable Size of a Step Disturbance in Linear Uncertain Systems
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Jayasuriya, S., and Sobhani, M. (December 1, 1994). "Frequency Domain Design for Maximizing the Allowable Size of a Step Disturbance in Linear Uncertain Systems." ASME. J. Dyn. Sys., Meas., Control. December 1994; 116(4): 635–642. https://doi.org/10.1115/1.2899262
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